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Name: Wenbin Hou

Type: User

Location: HangZhou, ZheJiang,China

Wenbin Hou's Projects

16-bit-hdlc-using-vhdl

High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.

16qam-decoder

Demodulates 16 Quadrature Amplification Modulation - Apparently.

16qam_project

Допилиавем по мере поступления задачи, связаннные с сооружением полного блока приёмника и источника сигнала

2016_person_re-id

TOMM2017 A Discriminatively Learned CNN Embedding for Person Re-identification

2fsk-2psk-2dpsk-qpsk-code-and-decode

用Verilog语言编写，实现2FSK，2PSK, 2DPSK, QPSK调制解调

this software is part of main project in Computer Architecture Laboratory which has been held in University of Tehran. for developing this project, i have used verilog Language in modelsim software. this project has been constructed, according to 5 staged MIPS pipeline (i.e. DesignSheet.jpg which included in the Design folder). the instruction set length of this project is 16 bit. the ALU of this Mips pipeline can do operation in Instruction Set of Type: R-Type Instruction set(register type: NOP, ADD, SUB, AND, OR, XOR, SL, SR, SRU, MUL) and I-Type Instruction set(Imediate Type: ADDI, LD, ST, BZ, JMP).

5g-polar-code

5g polar code

6502

Verilog implementation of a MOS6502 compatible CPU core.

8051

FPGA implementation of the 8051 Microcontroller (Verilog)

8051-tuner

3-octave tone generator using an 8051 MCU

8pointdct_verilog

Discrete Cosine Transform (DCT) is one of the important image compression algorithms used in image processing applications. Several algorithms have been proposed over the last couple of decades to reduce the number of computations and memory requirements involved in the DCT computation algorithm. One of the algorithms is implemented here using Verilog HDL.