AngeloJacobo/UberDDR3
Opensource DDR3 Controller
Good morning to you
Opensource DDR3 Controller
Vivado files for testing my SD card driver. Implemented on CMOD S7 FPGA.
My notes for DDR3 SDRAM controller
My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
Opensource DDR4 Controller
Bit-bang i2c protocol for interfacing with DS1307 RTC
Verilog design files and Icestudio file for Sobel Edge Detection with OV7670 camera using ULX3S FPGA Board
SDRAM controller optimized to a memory bandwidth of 316MB/s
Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps
Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board
FIFO implementation with different clock domains for read and write.
Config files for my GitHub profile.
This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow.
A simple DDR3 memory controller
10Gb Ethernet Switch
The core of the CaaS platform, configuration parser and Makefile generator
Hamming ECC Encoder and Decoder to protect memories
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
This contains my notes on how to customize existing Android apps such as changing app name, app icon, hiding app from the app drawer, and others.
ZipSTORM-MX, an iCE40 ZipCPU demonstration project
temporary repo
Demo projects for various Kintex FPGA boards
:snowflake: Icestudio examples - Community contributions
Just a collection of my python scripts