Blebowski/OpenChar
Open Source VLSI library characterizer
ASIC designer with interest in Embedded and EDA tools
Repositories
Blebowski/Reg_Map_Gen
Register map generator for VHDL digital designs and Embedded Systems.
Blebowski/ipyxact
Python-based IP-XACT parser
Blebowski/nvc
VHDL compiler and simulator
Blebowski/siliconcompiler
Modular hardware build system
Blebowski/CharLib
Open-source repository for a standard-cell library characterizer using complete open-source tools
Blebowski/hal
HAL – The Hardware Analyzer
Blebowski/PeakRDL-cheader
Blebowski/PeakRDL-uvm
Generate UVM register model from compiled SystemRDL input
Blebowski/OSVVM
OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
Blebowski/psl_with_ghdl
Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
Blebowski/PeakRDL-regblock
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
Blebowski/verilator
Verilator open-source SystemVerilog simulator and lint system
Blebowski/slang
SystemVerilog compiler and language services
Blebowski/qemu
Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.
Blebowski/vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
Blebowski/ghdl
VHDL 2008/93/87 simulator
Blebowski/llhd
Low Level Hardware Description — A foundation for building hardware design tools.