ChristianJacobsen/azerothcore-helm
Helm chart and images for AzerothCore: WoW WotLK (3.3.5a), vanilla or playerbots
Senior Firmware & FPGA Engineer @Zivid. Formerly @Integrikey, @cisco.
Helm chart and images for AzerothCore: WoW WotLK (3.3.5a), vanilla or playerbots
Helm chart and images for CMaNGOS: WoW Classic (1.12.1), TBC (2.4.3) and WotLK (3.3.5a)
Dynamic seedbox IP reporter for MyAnonaMouse
Share one serial port between several people, scripts and a log file
Rust bindings for COVESA Open1722 (IEEE 1722 / AVTP).
Talos Linux System Extensions
UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
A parametric aircraft geometry tool
Set up your GitHub Actions workflow with a OSS CAD Suite
A Rust implementation of Fly.io's Distributed Systems Challenge
A conversion of the 5etools Dungeons & Dragons 5th Edition Witcher Class for ReRoll
HTTP(S)-Server written in C conforming to RFC standards
Just another Flappybird clone...
Angular Chat Client using Sockets.IO