DamienLeBars/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
Virtual Platform Software developer
Repositories
DamienLeBars/pulp-sdk
DamienLeBars/riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC
DamienLeBars/Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.
DamienLeBars/UHDM
Universal Hardware Data Model
DamienLeBars/capnproto
Cap'n Proto serialization/RPC system - core tools and C++ library
DamienLeBars/UHDM-tools
DamienLeBars/nrt-sv-parsers
Non regression test: SystemVerilog parser