DustinWang1/rv32i-proc
5 stage pipelined processor from scratch. Implements RV32i.
5 stage pipelined processor from scratch. Implements RV32i.
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.
A launch point for your personal nvim configuration
Container CAD and PCB files for a guitar amp. Material and parts cost ~120.
Efficient implementations of state-of-the-art linear attention models in Pytorch and Triton
Config files for my GitHub profile.
Electrical Design Repository for fs-3 schematics and PCBs
ASR - ResCNN + BiGRU
Pytorch implementation of Conformer from "Conformer: Convolution-augmented Transformer for Speech Recognition". Uses rotary positional encoding instead though.
Automatic speech recognition model adapted from Attention is All You Need. Biggest difference is removing encoder input and replacing positional encoding with a residual CNN.
Collection of tutorials and stuff.
Electrical design repository for the FS-2 racecar
FS-2 control and bms code written using mbed 6
Blog for CP problems