Evensgn/RISC-V-CPU
RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
Lecture notes of Computer Architecture course, ACM Class, SJTU.
MPHD: a Model Pre-training method on Heterogeneous Domains
Python scripts to extend functions of personal WeChat accounts, using itchat. / 扩展个人微信账号功能的Python脚本,使用开源的WeChat的Python接口itchat。
Simulator of the five-stage pipeline to process MIPS instructions, written in C++
Some of my C++ container templates for Data Strucure 2017, ACM Honors Class, SJTU.
Designing automated market makers with differentiable economics and strong duality
Production repository for the all-new Advantage360 Professional using ZMK engine
A compiler for Mx* (a C-and-Java-like language)
OpenAI Baselines: high-quality implementations of reinforcement learning algorithms
TensorFlow GAN implementation using Gumbel Softmax
OCR for handwritten data forms.
Course material for "Numerical Methods for Data Science" (SJTU, summer 2018)
Toy Compiler for Compiler 2016 Course
Demo frontend for course project of Data Structure 2018 @ ACM Class
Frontend of software mirrors
The offline version of acm-compiler-judge
Fantasy Ptrace
My exercises answers of Scientific Computing course, 2017.
A railway ticket management system, group project for Data Structure 2017, ACM Class, SJTU.
SJTU Online Judge
Text classification on hotel comments, course work of PPCA 2017, ACM Class, SJTU.
Practice of recommender system, course work of PPCA 2017, ACM Class, SJTU.