LiWei

@HexSDR · User

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40 followers14 repositories

Repositories

HexSDR/uart2bus

整合了两个opencores.org和fpg4fun.com的两个开源项目,通过串口命令对总线进行读写的接口,适合用在fpga的debug查看内部寄存器或者信号。

★ 6VerilogForks 0

HexSDR/openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

★ 0CForks 0

HexSDR/openofdm_rx

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

★ 3Forks 0

HexSDR/linux

Linux kernel variant from Analog Devices; see README.md for details

★ 2Forks 1

HexSDR/openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

★ 1Forks 0