JeanRochCoulon/cva6
Ariane is a 6-stage RISC-V CPU capable of booting Linux
Repositories
JeanRochCoulon/tristan-unified-access-page
Unified Access Page for the TRISTAN project
JeanRochCoulon/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
JeanRochCoulon/riscv-extension-interface
JeanRochCoulon/programs
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
JeanRochCoulon/core-v-verif-ori
Implement the cv64 regression suite based on riscv-dv
JeanRochCoulon/tech_cells_generic
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
JeanRochCoulon/trial
JeanRochCoulon/axi_mem_if
Simple single-port AXI memory interface
JeanRochCoulon/riscv-dbg
RISC-V Debug Support for our PULP Cores