KedharGuhan/Pipelined-FPMAC-system
Course Project implemented on Nexus A7 FPGA
Repositories
KedharGuhan/project_code
KedharGuhan/driver_drowsiness_system_CNN
This is a system which can detect the drowsiness of the driver using CNN - Python, OpenCV
KedharGuhan/A-convolution-kernel-implemented-by-Vivado-HLS
This project implements a convolution kernel based on vivado HLS on zcu104
KedharGuhan/vivado_hls_img_proc
Source codes for High Level Synthesis for Fixed Progammable Gate Arrays (FPGAs). Can be converted to RTL using Vivado HLS or SDSoC.
KedharGuhan/matmul-2020.2
A floating-point matrix multiplication implemented in hardware
KedharGuhan/PYNQ_tutorials
KedharGuhan/cnn-facial-landmark
Training code for facial landmark detection based on deep convolutional neural network.
KedharGuhan/Accelerating-CNN-with-FPGA
This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.
KedharGuhan/Face_detection_HLS
with maxi port
KedharGuhan/HLS-CNN
High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
KedharGuhan/CNN-using-HLS
Convolutional Neural Network Using High Level Synthesis
KedharGuhan/lenet5_hls
FPGA Accelerator for CNN using Vivado HLS
KedharGuhan/RP2040-Verilog-Design
KedharGuhan/fpga_pio
An attempt to recreate the RP2040 PIO in an FPGA
KedharGuhan/Introduction-to-SoC-Design-Education-Kit
Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedded programs targeted at the microprocessor to control the peripherals
KedharGuhan/xup_high_level_synthesis_design_flow
AMD Xilinx University Program HLS tutorial
KedharGuhan/Digital-Design-of-FIR-Filter
Hardware Design and Verification of a configurable and parametrized 50th order low-pass FIR filter starting from MATLAB Modeling to Verilog RTL Design and Simulink Testing with .wav audio files.
KedharGuhan/nandland
All code found on nandland is here. underconstruction.gif
KedharGuhan/FloatingPointMAC_with_FIFO_on_FPGA
This digital design project was created for the course EE271 in SJSU.
KedharGuhan/tweak_circuits
Tweak circuits designed in VHDL/Verilog like CDC synchronizers: Pulse synchronizer, Reset synchronizer, Two-flop synchronizer, Edge detectors, Pulse generators, Clock gating etc.
KedharGuhan/reset_and_cdc_synchronizers
Reset and CDC synchronizers developed in Verilog/System Verilog.
KedharGuhan/FIFOs
Register-based and RAM-based FIFOs designed in Verilog/System Verilog.
KedharGuhan/tutorialsOnVerilog
KedharGuhan/Pipeline-CPU-mips32
基于MIPS32指令集（部分指令）的五级流水线CPU。验证方法：使用指令跑通了斐波那契数列（可用寄存器指定项数）。
KedharGuhan/PoC
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
KedharGuhan/Shor-s-Algorithm_Quantum
R.I.P - RSA_cryptography (1977-2019)
KedharGuhan/Artix_7
My experiments with Nexys4 DDR Artix-7 FPGA Board
KedharGuhan/Rubiks_Cube_Solver_Algorithm
This is a C++ program that implements the Layer-Wise method to solve a 3×3×3 Rubik’s Cube in under 800 lines of code.
KedharGuhan/qiskit-textbook
A university quantum algorithms/computation course supplement based on Qiskit