Repositories
LarsAsplund/open-source-fpga-resource
A list of resources related to the open-source FPGA projects
LarsAsplund/vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
LarsAsplund/github-facts
GitHub-based statistics highlighting interesting facts about the HDL industry
LarsAsplund/synchronization
Synchronization mechanisms for VHDL
LarsAsplund/a2i
LarsAsplund/JSON-for-VHDL
A JSON library implemented in VHDL.
LarsAsplund/OSVVM
Open Source VHDL Verification Methodology (OSVVM) Repository
LarsAsplund/neorv32
A size-optimized, customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
LarsAsplund/microwatt
A tiny Open POWER ISA softcore written in VHDL 2008
LarsAsplund/udp_ip_stack
UDP IP stack example project from this VUnit getting started blog (https://www.linkedin.com/pulse/vunit-best-value-initial-effort-lars-asplund)
LarsAsplund/vunit_attributes
Demonstrate VUnit attributes
LarsAsplund/gha_tests
Playing around with GHA
LarsAsplund/vhdl2008-tester
Scripts to test which features from VHDL 2008 are supported by your compiler.
LarsAsplund/splitting_signals
LarsAsplund/Compliance-Tests
LarsAsplund/tb_drain_strategy
LarsAsplund/Playground
Develop the directors structure and testing infrastructure for CoreLib
LarsAsplund/CoreLib
A VHDL Core Library.
LarsAsplund/matlab_integration
Example of VUnit Matlab integration