Steinegger/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Repositories
Steinegger/riscv_asconp_accelerator_core
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Steinegger/ariane-sdk
Ariane SDK containing RISC-V tools and Buildroot
Steinegger/riscv_asconp_accelerator
Meta repo, Ascon-p instruction for RISC-V
Steinegger/riscv_asconp_accelerator_isa_sim
Spike, a RISC-V ISA Simulator
Steinegger/vivado-lxc
Launch an Ubuntu lxc container and install Xilinx Vitis/Vivado
Steinegger/riscv_asconp_accelerator_software
Ascon implementation utilizing the Ascon-p instruction for RISC-V
Steinegger/edalize
An abstraction library for interfacing EDA tools
Steinegger/vivado-docker
Dockerfile with Vivado for CI