Comments (1)
Comment by whitequark
Tuesday Jun 11, 2019 at 03:48 GMT
@sbourdeauducq Here's the major obstacle to getting this done: instance ports. Inout and in ports can in principle be ignored (though that raises the question of whether we're going for full correctness or best-effort detection), but all out ports would require some annotation or they'd just emit false violations. I'm not sure how to best handle this yet.
Maybe the platform could provide an annotated list of primitives? But that doesn't help external Verilog.
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