Related Issues (20)
- Plans for the next release? HOT 1
- How to adding a new component ? HOT 16
- docs: Document Case, FSM HOT 1
- module ports in generated verilog doesn't have names HOT 1
- Implement RFC 2: Interface definition library
- Implement RFC 18: Reorganize vendor platforms HOT 2
- Implement RFC 19: Remove `amaranth.lib.scheduler`
- Implement RFC 20: Deprecate and remove non-FWFT FIFOs
- Implement RFC 22: Add `ValueCastable.shape()`
- Deprecate `Record`
- Unfriendly "recursion depth exceeded" error message when forgetting `In` and `Out` on a `Component`'s signature HOT 2
- Infer Verilog ports on Interface objects HOT 1
- Memory generates an empty Verilog wrport module that Vivado considers a black box HOT 6
- Use something better than `path=` in `Interface()`/`Signature.create()`
- `amaranth.lib.enum` does not support functional syntax
- Signal reset cannot be set to a const value
- Possible inconsistency in FlippedSignature HOT 2
- `lib.wiring.connect` does not take custom `Signature.__eq__` overrides into account HOT 2
- agregate Signal() HOT 1
- Issue with `Memory` simulation HOT 2
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