Comments (6)
@kabrodzki I made a fork. You should be able to push there.
As for more info about the DMA you can always ask the author @piotr-binkowski
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I don't know if this will be useful, but LiteX is able to convert the AXI to wishbone:
https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/axi.py#L403
But this is like a wrapper on a wrapper, so maybe there is a better option.
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Can we fork this fastVDMA project? After some quick test I see that we need to change the configuration to use the Wishbone, because now it's generating the verilog source for AXI4
DMATop.scala:
val csrFrontend = Module(new AXI4LiteCSR(DMATop.addrWidth))
val readerFrontend = Module(new AXIStreamSlave(DMATop.addrWidth, DMATop.readDataWidth))
val writerFrontend = Module(new AXI4Writer(DMATop.addrWidth, DMATop.writeDataWidth))
I am also not quite sure how can we test the wrapper alone. I remember that @kgugala mentioned that there is some more extensive paper on this project (I mean more extensive than this and this)
from 2d-gpu.
I created the repo for the wrapper and uploaded the "Link layer", but I'm not quite sure how to go from there.
from 2d-gpu.
now you should include the DMA in the LiteX system you're working on, so you can access DMA's registers from the CPU
from 2d-gpu.
you will also need to wrap your wishbone signals as wishbone.Interface()
(like here) so that you can later use them with add_wb_master
and add_wb_slave
in your target.
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Related Issues (11)
- Run Litex/VexRiscv system on Arty HOT 3
- FastVDMA Wishbone configuration HOT 3
- Run LiteX on ArtyA7 HOT 17
- FastVDMA tests HOT 1
- Blender HOT 9
- Add the rest of the team HOT 1
- Help #1 HOT 10
- Get familiar with the tools
- Help #2 HOT 9
- Contribution rules - CONTRIBUTING.md
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