About pipeline view in paper DAC'23 about charm

[JinmingZhuang]

Hi,

Thank you for reaching out.

1. For the A_BRO and C_BRO setup. The A_BRO and C_BRO are the broadcast tuning factors for left-hand-side (LHS) operands and right-hand-side (RHS) operands to alleviate the routing congestion. Take A * B * C AIE array for Matrix Multiply (MM) as an example, the row of LHS can be broadcast to every column in RHS. In this case, A_BRO can be set up to "C" and also can be a factor of C.

2. For the AIE simulation test data, currently we don’t have an automatic data generator for all the cases in the Github repo. However, I could point you to how to generate the correct format.
   • The test data is determined by the PLIO port width together with the data type of the kernel which is described in this section: https://docs.xilinx.com/r/2021.1-English/ug1076-ai-engine-environment/Simulation-Input-and-Output-Data-Streams.
   • For packet-switch cases, users should further add a header and a TLAST flag to the test file which can be viewed in this example: https://github.com/Xilinx/Vitis-Tutorials/blob/2023.2/AI_Engine_Development/AIE/Feature_Tutorials/04-packet-switching/buffer_based_aie_kernel.md.

Hope these answers will be helpful.