Comments (1)
If we go down the path of generating a function that returns a field's name given the field's bit position, I foresee the following complexities:
- Some fields are 1 bit, some fields are a range of bits
- Registers have a name (sort of a like a weak "id") and a long name (a more human-readable version, if defined)
- Some registers have more than one fieldset. In other words, you must decide how to interpret the register's contents based on external factors (e.g. this CPUID leaf)
This sounds possible, but I'm wondering if there is another more general approach to tackle the immediate problem you face: printing a human-friendly message when a semantic constraint is violated about a CPU's usage. What do you think about the idea outlined in Discussion #82?
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Related Issues (20)
- Component header error HOT 4
- [RFC] Shoulder Gadgets HOT 3
- Decorator Based Gadgets HOT 3
- External Access Mechanism Code Generation
- Coprocessor Register Access Mechanism Code Generation
- Banked System Register Access Mechanism Code Generation
- Vector/SIMD Control Register Access Mechanism Code Generation
- System Register Immediate Access Mechanism Code Generation HOT 1
- Update C Header Generator HOT 1
- README
- YAML Data Generator
- Initial VMCS Support
- Encoding-based access mechanism writer HOT 1
- Missing info target HOT 1
- [BUG] VMCS access mechanisms fail for fields that aren't 64-bits HOT 1
- Generator Modules HOT 4
- RFC: PAL Instruction APIs HOT 2
- RFC: PAL Project Ownership/Maintenance HOT 16
- Documentation writers for C and C++
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