BrianHG's Projects
FPGA based USB 2.0 high speed audio interface featuring multiple optical ADAT inputs and outputs
A Verilog I2C initializer with integrated RS232 debugger. *** New v1.1 Supports I2C CLK stretch and separate IO buffers for driving Efinix's IO primitive.
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
Config files for my GitHub profile.
Collaborative project to create an advanced GPU for the Microcom computer.
Testbench for ' https://github.com/nockieboy/gpu ' geometry engine. Draw pixels, lines, boxes, triangles, quadrilaterals, ellipses, filled option, blitter scale and flip/mirror/rotate graphics and save the results as a .bmp picture for inspection.
Send video/audio over HDMI on an FPGA
Minimig for SoCkit (MiSTer)
SystemVerilog HDMI encoder, serializer & PLL generator. Tested on Cyclone IV-E, Compatible with Quartus 13.0 through Quartus Prime 20.1.
This example .BMP generator and ASCII script file reader can be adapted to test code such as pixel drawing algorithms, picture filters, and make use of a source ascii file to drive the inputs of your .sv DUT module while offering logging of the results, and executing the list of commands in order.
Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter using fractional floating point division.
Verilog RS232 Enhanced Synch-UART & RS232 Debugger HDL core with PC host RS232 real-time Hex-editor / viewer host utility.
YM2149 / AY-3-8910 Programmable Sound Generator. Offers dual PSGs, programmable stereo mixer with bass and treble controls, standard I2S 44.1KHz or 48KHz 16-bit digital audio out, and built in floating point system clock divider/generator.
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