ARM AArch32 instruction ADD may decode wrong in ADR situation about capstone

[yakamoz423]

This is an LLVM bug as it turns out:

echo "0x24,0xca,0x8c,0xe2,0x00,0xc6,0x8f,0xe2" | llvm-mc-19 --triple=arm --disassemble
	.text
	add	r12, r12, #36, #20
	add	r12, pc, #0, #12

Same for llvm-mc-18. Could you please open an issue with LLVM?

I post on llvm/llvm-project#93930

[yakamoz423]

Another case:

0xe28cca24

Should be:

ADD, ADDS (immediate) - A1

But result with cstool:

 0  e2 8c ca 24  add    r12, r12, #36, #20
        ID: 31 (add)
        op_count: 4
                operands[0].type: REG = r12
                operands[0].access: WRITE
                operands[1].type: REG = r12
                operands[1].access: READ
                operands[2].type: IMM = 0x24
                operands[2].access: READ
                operands[3].type: IMM = 0x14
                operands[3].access: READ
        Registers read: r12
        Registers modified: r12
        Groups: IsARM

Got an unexpected imm op[3], which seems not be expanded (rotr op[2] by op[3]).

[Rot127]

This is an LLVM bug as it turns out:

echo "0x24,0xca,0x8c,0xe2,0x00,0xc6,0x8f,0xe2" | llvm-mc-19 --triple=arm --disassemble
	.text
	add	r12, r12, #36, #20
	add	r12, pc, #0, #12

Same for llvm-mc-18. Could you please open an issue with LLVM?