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captainliuy's Projects

awesome-hpp icon awesome-hpp

A curated list of awesome header-only C++ libraries

awesome-python icon awesome-python

A curated list of awesome Python frameworks, libraries, software and resources

axorderbook icon axorderbook

A股订单簿工具,使用逐笔行情进行订单簿重建、千档快照发布、各档委托队列展示等,包括python模型和FPGA HLS实现。

chainsaw icon chainsaw

a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communication and Crypto applications

cocotb icon cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

concurrentqueue icon concurrentqueue

A fast multi-producer, multi-consumer lock-free concurrent queue for C++11

crcgen icon crcgen

Generator for CRC HDL code (VHDL, Verilog, MyHDL)

doctest icon doctest

The fastest feature-rich C++11/14/17/20 single-header testing framework

fakeit icon fakeit

C++ mocking made easy. A simple yet very expressive, headers only library for c++ mocking.

hlslib icon hlslib

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

ntl icon ntl

Networking Template Library for Vivado HLS

open-rdma icon open-rdma

RoCE v2 hardware implementation using Spinal HDL

peakrdl icon peakrdl

Control and status register code generator toolchain

pollnet icon pollnet

A collection of non-blocking(polling) network libs for Linux, also support solarflare APIs(Tcpdirect/Efvi)

rudp icon rudp

rudp 是在UDP上实现的可靠传输(rudp is a reliable transmission on UDP)

veriloggen icon veriloggen

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

wb2axip icon wb2axip

Bus bridges and other odds and ends

xkisp icon xkisp

xkISP:Xinkai ISP IP Core (HLS)

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