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act

ACT hardware description language

aes

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

aes-256-bit-encryption-algorithm

VHDL design of AES-256 bit encryption algorithm with 6 button push authentication, implemented on spartan 6 FPGA

aesio

Lightweight and portable AES-128/192/256 API implementation in C.

amc

AMC: An Asynchronous Memory Compiler

arv

ARV: Asynchronous RISC-V Go High-level Functional Model

ascend-freepdk45

A free standard cell library for SDDS-NCL circuits

astran

ASTRAN - Automatic Synthesis of Transistor Networks

async-click-library

asynchronous-fifo

Asynchronous fifo in verilog

avs_aes

Avalon AES ECB-Core (128, 192, 256 Bit)

balsa-aes-core

Asynchronous AES core written using the Balsa hardware description language

basic_verilog

Must-have verilog systemverilog modules

bsg_manycore

Tile based architecture designed for computing efficiency, scalability and generality

decode

e200_opensource

The Ultra-Low Power RISC Core

genesis2

A home for Genesis2 sources.

hello-world

just another version

kamikaze

Light-weight RISC-V RV32IMC microcontroller core.

lichen

Library Characterization Environment (LiChEn)

lichen-1

Library Characterization Environment - Open source tool for Cell Library Characterization

network-on-chip-demo

A hardware design of 2-dimensional torid network with 16 circuit-switched router nodes

pci_blue_interface

No description

riscv

RISC-V CPU Core (RV32IM)

rocket

sm4-sbox

Verilog Implementation of SM4 s-box

sphinx_hierarchical_formal_verification

SPHINX is a design verification tool for asynchronous circuits and systems which has the capability of verifying speed independence and conformance of asynchronous circuits to their specifications. The original source code of this project is reposited as-is on Github. For more information about this project please visit: http://async.usc.edu/index.php/research/8-research/8-sphinx

uhd

The USRP™ Hardware Driver Repository

vscale

Verilog version of Z-scale (deprecated)

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