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32-verilog-mini-projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

artix-7-hdmi-processing

Receiving and processing 1080p HDMI audio and video on the Artix 7 FPGA

axi4_interconnect

AXI总线连接器

axi_ethernet_bridge

A bridge IP for interconnecting Xilinx's AXI Ethernet Subsystems (used with EthernetFMC).

biriscv

32-bit Superscalar RISC-V CPU

bsq

BSQ: Exploring Bit-Level Sparsity for Mixed-Precision Neural Network Quantization (ICLR 2021)

charm

CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture (Full Paper accepted to FPGA2023!)

chengquan.github.io

Github Pages template for academic personal websites, forked from mmistakes/minimal-mistakes

chengquantool

cnn-detect-facial-keypoints

Using Convolutional network for detection of facial keypoints

core_ddr3_controller

A DDR3 memory controller in Verilog for various FPGAs

core_sdram_axi4

SDRAM controller with AXI4 interface

cuda-cnn

CNN accelerated by cuda. Test on mnist and finilly get 99.76%

cuda-mcdnn

cuda_cnn

Various version (CPU, CUDA_NAIVE, CUDA_TILED, GEMM) convolutional neural network implementations by Heechul Lim

custom-analog-design-flow-tutorial

The goal of this tutorial is to get you introduced to custom analog design flow using Synopsys Custom Design Platform. This tutorial uses Synopsys tools such as Custom Compiler, PrimeWave Design Environment, PrimeSim Continuum, IC Validator, StarRC, and is based on an OPAMP design that uses Synopsys 14nm Interoperable PDK. Some of the main topics c

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

deepin-wine-ubuntu

Deepin wine for ubuntu

dl_accelerator

Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions

dnnweaver2

Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.

e203_hbirdv2

The Ultra-Low Power RISC-V Core

elf

ELF: a platform for game research with AlphaGoZero/AlphaZero reimplementation

ethernet-fmc-axi-eth

Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks

faster-rcnn.pytorch

A faster pytorch implementation of faster r-cnn

faster_rcnn

Faster R-CNN

flash-linux0.11-talk

你管这破玩意叫操作系统源码 — 像小说一样品读 Linux 0.11 核心代码

fpga_eth_dual_ov5640

fpga读取摄像头数据上传到上位机，720P@60Hz

fpgamp

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

fq-vit

[IJCAI 2022] FQ-ViT: Post-Training Quantization for Fully Quantized Vision Transformer

fq-vit-test

所有代码均基于https://github.com/megvii-research/FQ-ViT修改