VeeR EL2 core is broken about sv-tests

[tgorochowik]

Hi Mike,

thanks for the report, we've disabled the UVM test for this core as it required a custom UVM branch anyway (it uses a custom branch anyway).

Some of the tools already pass this test (slang fails though).

[MikePopoloski]

After the UVM changes the slang failures look like this:

../../../third_party/cores/veer-el2/testbench/tb_top.sv:1304:16: error: cannot have multiple continuous assignments to variable 'dccm_wr_data_bank'
        assign el2_mem_export.dccm_wr_data_bank[i] = dccm_wr_fdata_bank[i][pt.DCCM_DATA_WIDTH-1:0];
               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../../../third_party/cores/veer-el2/testbench/tb_top.sv:793:30: note: also assigned here
    .dccm_wr_data_bank      (el2_mem_export.dccm_wr_data_bank),
                             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

These appear to be real errors to me, not sure why other tools are not catching this. I believe this is related to this other issue in your project's tracker: chipsalliance/Cores-VeeR-EL2#163