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cisen's Projects

4_bit_rpn_calculator icon 4_bit_rpn_calculator

A multisim project using counters, multiplexers, RAM chips, and ALUs to create an RPN calculator

acore icon acore

Asynchronous OS kernel written in Rust.

android-chat icon android-chat

[飞享]-全开源即时通讯(IM)系统的Android客户端,底层协议栈使用Java NIO进行完全自主改造,全新的心跳设计,全新的二进制协议设计,支持与[飞享] Web客户端消息互通。支持文本,语音,视频等常用功能

angular-rxjs icon angular-rxjs

Sample Angular application that uses RxJS for reactive development. Find the associated Pluralsight course here: https://app.pluralsight.com/library/courses/rxjs-angular-reactive-development/table-of-contents

artix-dc-scm icon artix-dc-scm

Experimental Xilinx Artix-7 driven Data Center Security Communication Module

bapi-rv32i icon bapi-rv32i

A extremely size-optimized RV32I soft processor for FPGA.

basic-charge-pump icon basic-charge-pump

一个电荷泵升压电路的基本实现,包含一个MOS高端驱动分立元件原理说明multisim仿真文件

basic-simd-processor-verilog-tutorial icon basic-simd-processor-verilog-tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

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