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csl-ku's Projects

bru-firesim icon bru-firesim

BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors

bwlock icon bwlock

A lock-like mechanism for protecting memory performance critical sections of SRT in MCPs

firechip icon firechip

Top-Level Project for Firebox SoC, consisting of Rocket, NVDLA, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.

firesim-nvdla icon firesim-nvdla

FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud

firesim-software icon firesim-software

Automatically Builds a Linux Distribution for FireSim/FireChip Nodes, works with FireSim's automatic workload generation.

isolbench icon isolbench

A set of synthetic benchmarks used in IEEE RTAS 2016 paper by Prathap et al.,

midas icon midas

FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL

spectreguard icon spectreguard

Data-centric defense mechanism against Spectre attacks. (DAC'19)

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