Generate timing diagram about scdlang

[brucou]

My background is electrical engineering so it might get influence from that. There are several way to analyze FSM in ASIC design (see [here](FSM-viz Verilog)). Let's move the discussion in #27.

Yeah I had a look at the link. It is true that chips are on a clock, so it makes sense to visualize it that way. Did you ever heard about Lucid Synchrone or Esterel? Those are synchronous languages compiling to fsm with model checking and all the jazz. They embed a notion of clock and use clocked streams for everything.

For the FSM I deal with, I think the interesting information for tracing is the sequence itself , i.e. instead of visualizing [(x_i, t_i] i.e. a sequence of x occurring at time t it is more interesting to visualize just the [x_i] directly on the graph visualization. But I haven't given too much thoughts to that.