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eblot avatar eblot commented on August 24, 2024

I'm not sure how to interpret the above screenshot, as the SCL signal seems weird.

  1. First L-H-L pulse is definitely a glitch, it is very hard to avoid them with the way FTDI works, but it should not be an issue
  2. Second L-H-L pattern looks like the ACK from read, which the master (here: FTDI) should emit
  3. NACK (at the end of the last received byte) is not seen, as expected
  4. the last L-H-L pattern looks like a STOP condition, but as SCL does not seem to return to full H level, this is weird.

from pyftdi.

eblot avatar eblot commented on August 24, 2024

I do not know how to reproduce this issue.

I'm wondering: does the slave use clock stretching (i.e. maintain SCL low)? This feature is not implemented in PyFTDI for now...

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