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apb_efuse_if

APB based interface to eFUSE macros

apb_pwm

Pulse Width Modulator programmed through an Advanced Peripheral Bus interface

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

ariane-wrapper

Wrapper for ETH Ariane Core

axi

AXI4 and AXI4-Lite synthesizable modules and verification infrastructure

berkeley-hardfloat

bigpulp

RISC-V manycore accelerator for HERO, bigPULP hardware platform

block-inclusivecache-sifive

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

chisel3

Chisel 3: A Modern Hardware Design Language

clint

RISC-V Core Local Interrupt Controller (CLINT)

common_cells

Common SV components

cores-swerv

SweRV EH1 core

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

dbg_interface

SoC Debug Interface

des

DES/Triple DES IP Cores

dma_ahb

AHB DMA 32 / 64 bits

dma_axi

AXI DMA 32 / 64 bits

dsptools

A Library of Chisel3 Tools for Digital Signal Processing

example-l2pm

Example code to demonstrate usage of Sifive L2 performance monitor counters to capture L2 cache event logs.

f32c

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

firrtl

Flexible Intermediate Representation for RTL

fpga19-moms

fpl19-dynaburst

fpnew

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

fpu

fpu_div_sqrt_mvp

[UNRELEASED] FP div/sqrt unit for transprecision

fpu_interco

gemmini

Berkeley's Systolic Array Generator