TIMG interrupt setup confusion about esp-hal

[bjoernQ]

Putting naming aside though, it also seems strange to me that the API allows you to initialise the wrong timer group's interrupts.

Totally agree - if that would get cleaned up the naming should be as simple as timer0, timer1 and wdt

[Dominaezzz]

Yeah the names are little confusing.

I suppose this might've been a little clearer?

let isr = TimerInterrupts {
  group0_timer0: Some(handler0),
  group0_timer1: Some(handler1),
  ..Default::default()
}

Putting naming aside though, it also seems strange to me that the API allows you to initialise the wrong timer group's interrupts.

let isr = TimerInterrupts {
  group0_timer0: Some(handler0),
  group0_timer1: Some(handler1),
  ..Default::default()
}

let timg1 = TimerGroup::new(
    peripherals.TIMG1,
    &clocks,
    Some(isr),
);

The above code, I create a driver for timer group 1 but I initialised the isr for timer group 0.

The API should probably just look something like this.

let isr = TimerInterrupts {
  timer0: Some(handler0),
  timer1: Some(handler1),
}

let timg1 = TimerGroup::new(
    peripherals.TIMG1,
    &clocks,
    Some(isr),
);

Then you can't specify the wrong group.

(Feel free to PR a name change if you like, though I'll probably do it this evening if no one else gets to it first)

[akriese]

Thanks for the quick reply! The thing is, that the ESP32 manual states, that there are T0 and T1 interrupts for EACH timer in each group. What does that even mean?

I agree with you that the API is probably not correct there. Your change to TimerInterrupts is what I would have imagined. But I wouldnt want to change anything there unless the above documentation weirdness can be ignored

[Dominaezzz]

Ah yes I see what you're saying. If we expand n and x we get.

TIMG0_T0_INT_T1_INT
TIMG0_T0_INT_T0_INT
TIMG0_T1_INT_T1_INT
TIMG0_T1_INT_T0_INT
TIMG1_T0_INT_T1_INT
TIMG1_T0_INT_T0_INT
TIMG1_T1_INT_T1_INT
TIMG1_T1_INT_T0_INT

Which seems rather strange. I reckon it's a typo but I'll leave this to the espressif devs to clarify. At a glance I don't spot anything that justifies the two interrupts.

Even knowing this, T0 and T1, whatever their uses may be, they'll be handled by the same handler. So while there may be two interrupts per timer, there's only one handler per timer.

[Dominaezzz]

esp-idf seems to agree with me about the typo https://github.com/espressif/esp-idf/blob/0479494e7abe5aef71393fba2e184b3a78ea488f/components/soc/esp32/include/soc/timer_group_reg.h#L556

So that doc should say

• TIMGn_WDT_INT: Generated when a watchdog timer interrupt stage times out.
• TIMGn_Tx_INT: An alarm event on timer x generates this interrupt.