Related Issues (20)
- Feature Request: VFAT Numbering Matches Current Convention
- Feature Request: Unify Address Table Format
- Ability to determine which clock is currently driving the TTC decoder
- Bug Report: sca.py wipes FW of all FPGA's regardless of link Mask HOT 4
- Bug Report: GEM_AMC Address Table Does Not have XInclude Lines HOT 1
- Bug Report: Divergence Between scripts on CTP7 and XHAL used in Central Repo
- Request: Change TTC_HARD_RESET_EN Default to 0x0 in v3.X.Y FW Releases
- [bug] generate_registers.py generates an invalid `uhal` address table for the BLASTER RAM HOT 4
- [Version 3.7.0] Address tables only contain 12OH's HOT 1
- [Version 3.7.0] Trigger links are always reported in an healthy state HOT 1
- [feature request] Package scripts into RPM for installation
- GE2/1 OH promless programming HOT 6
- VFAT & AMC BX Mismatch no longer set to 0 automatically
- Drop `BxmAvO` and Add VFATX vs. VFATY Mismatch Flags in FW & Event Format HOT 2
- [bug] UHAL address tables generated incorrectly HOT 3
- [Version 3.8.3] Sbit monitor always reports wrong clusters HOT 1
- New Bug in UHAL Address Tables? HOT 11
- Potential Bug When Writing GEM_AMC.SLOW_CONTROL.SCA.CTRL.TTC_HARD_RESET_EN Post 3.8.4?? HOT 3
- Adding gbt_ic_controller Read Capability Disscussion
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