Comments (4)
Right now many vector instructions will also use the destination register as a source to implement the tail/mask undisturbed policy. Currently it's the default even if you set agnostic behavior for both, but #1135 should fix this.
from gem5.
Thx for your explanation.
So, there isnt any option to change that policy without modification right now, am I right?
from gem5.
No. The mentioned PR adds in this option, without it gem5 will always assume an undisturbed policy for both tail and mask, even if you specify otherwise with ta ma
in your vset{i}vl{i}
instruction.
from gem5.
I am transitioning this into a discussion. If I am mistaken and there is a real bug that needs to be fixed, please let me know. Thanks.
from gem5.
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from gem5.