Comments (1)
The following is the screenshot comparing the expected commit trace (on the left) and the commit trace produced by O3 CPU (on the right). It looks like the problem was at csrrw
instruction's execution.
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Related Issues (20)
- How can I specify in the configuration file or command line that my simulation can wait for remote GDB connections before starting simulation HOT 4
- Fix daily tests failing due to removing gcn3_x86 HOT 7
- RISCV RVV vfredmax.vs and vfredmin.vs implementation is incorrect HOT 2
- RVV instruction vmem faults caused by incorrect vl HOT 1
- CLFLUSH causes TLB assertion error HOT 1
- X86KvmCPU + se.py + mem-size ≥4 GB causes crash
- X86KvmCPU floating point exceptions when executing x87 FPU instructions
- arch-riscv: return values of m5 pseudo instructions in 32 bit systems HOT 7
- CHI (Arm) near/far atomic operation causes deadlock HOT 9
- Replace bitmanip test cases of asmtest resources with upstream one HOT 1
- arch-riscv: remove branching from `vset{i}vl{i}` instruction and allow registers `vl` and `vtype` to be renamed HOT 6
- arch-x86: bug in movss instruction HOT 5
- Test support for Ubuntu 24.04 HOT 3
- arch-x86,O3,KVM switching to full simulation bug HOT 4
- Simple question about custom instruction implementation HOT 1
- Linking Error when enable AddressSanitizer HOT 6
- Bug in restoring a checkpoint using SimpleProcessor and SwitchableProcessor in ARM & KVM setup HOT 6
- gem5::statistics::Counter are 52-bit not 64-bit HOT 3
- Immediate crash when running KVM CPU in SE mode HOT 2
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