Comments (6)
Certainly some of these are problematic, but
CLASS core SPACER ;
CLASS core WELLTAP ;
are totally valid. See grammar from the LEF/DEF spec. https://www.ispd.cc/contests/18/lefdefref.pdf page 172
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And +1 to Ethan. Philipp: Make sure you're looking at the 5.7 or 5.8 spec. The requirement of a single value for CLASS is from 5.4 or something; not exactly sure when they added the optional 2nd argument.
But clearly these issues come from a sloppy application of string replacement, where the original cell names "TIEL", "TIEH", "ENDCAP", and "ANTENNA" (the last one noted by Philipp in a later issue) are cell names that are replaced by the open PDK equivalents, but they are also valid LEF keywords.
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@RTimothyEdwards or @thesourcerer8 I'm not near a keyboard where I could make this change would either of you mind making a PR to fix this?
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@QuantamHD : These fixes have already been made on the efabless fork. You need to get a pull request from our fork.
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Does google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0#23 look right?
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As far as I can tell, this didn't affect the mcu7t5v0
library.
tansell@tansell-glapstation:~/github/google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0$ grep -R 'CLASS' | grep -v 'core ;' | grep -v 'core SPACER ;'
cells/tieh/gf180mcu_fd_sc_mcu7t5v0__tieh.lef: CLASS core TIEHIGH ;
cells/endcap/gf180mcu_fd_sc_mcu7t5v0__endcap.lef: CLASS ENDCAP PRE ;
cells/antenna/gf180mcu_fd_sc_mcu7t5v0__antenna.lef: CLASS core ANTENNACELL ;
cells/filltie/gf180mcu_fd_sc_mcu7t5v0__filltie.lef: CLASS core WELLTAP ;
cells/tiel/gf180mcu_fd_sc_mcu7t5v0__tiel.lef: CLASS core TIELOW ;
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Related Issues (20)
- Standard cell reference missing for DLATCH in gf180 PDK HOT 6
- CLASS core confusion HOT 8
- Wrong commands in LEF file HOT 9
- "View" and "Edit" links in documentation don't work HOT 1
- Missing "Generated Layer and Generation rules" section
- Missing design rules? HOT 5
- incorrect diagram in lvs_bjt page
- Create OpenRCX enablement HOT 1
- Resistor Model issue
- liberty files are missing default_fanout_load
- Standard cell page in the docs is broken HOT 7
- MOSFET Multipliers not accounted for, in SPICE Simulation HOT 13
- How to use gf180mcu-pdk into openlane flow? HOT 10
- Missing Blocker Label to identify show stoppers for progress on platform against this Repo HOT 1
- Update ngspice regression tests README to include information about how to interpret the results HOT 1
- Update xyce regression tests README to include information about how to interpret the results HOT 1
- sdff* cells are not parseable by yosys HOT 1
- Create corner tech lefs with updated via/layer resistances
- Public DRM does not render correctly, is hard to navigate HOT 1
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