gregac / ibex_super_system Goto Github PK
View Code? Open in Web Editor NEWIbex Super System is DEPRECATED, and has become the Ibex Demo System: https://github.com/lowRISC/ibex-demo-system which is maintained by lowRISC.
License: Apache License 2.0
ibex_super_system's People
Contributors
Stargazers
Watchers
Forkers
sundarapandian patrickerich snematbakhsh c-riscv ctopal longstudy trellixvulnteam marnovandermaasibex_super_system's Issues
Unable to connect OpenOCD
Hi,
I have been trying to implement the super-system on an Artix-7 AC701 board. I was able to synthesize, implement and program the FPGA with a slightly modified design (lower number of GPIOs and different clock generation) and pin constraints. But when trying to connect the design with OpenOCD via JTAG, I get the following error (output when run with the -d3 flag):
$ ./util/load_super_system.sh halt ./sw/build/demo/demo
xPack OpenOCD x86_64 Open On-Chip Debugger 0.11.0+dev (2022-09-01-17:56)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
User : 3 1 options.c:52 configuration_output_handler(): debug_level: 3
User : 4 2 options.c:52 configuration_output_handler():
Debug: 5 2 options.c:233 add_default_dirs(): bindir=bin
Debug: 6 2 options.c:234 add_default_dirs(): pkgdatadir=
Debug: 7 2 options.c:235 add_default_dirs(): exepath=/net/home/vaidyanathan/Prebuilt/xpack-openocd-0.11.0-5/bin
Debug: 8 2 options.c:236 add_default_dirs(): bin2data=../
Debug: 9 2 configuration.c:33 add_script_search_dir(): adding /net/home/vaidyanathan/.config/openocd
Debug: 10 2 configuration.c:33 add_script_search_dir(): adding /net/home/vaidyanathan/.openocd
Debug: 11 2 configuration.c:33 add_script_search_dir(): adding /net/home/vaidyanathan/Prebuilt/xpack-openocd-0.11.0-5/bin/..//site
Debug: 12 2 configuration.c:33 add_script_search_dir(): adding /net/home/vaidyanathan/Prebuilt/xpack-openocd-0.11.0-5/bin/..//scripts
Debug: 13 2 command.c:155 script_debug(): command - ocd_find /net/home/vaidyanathan/Projects/ibex_super_system/util/a7-ac701-openocd-cfg.tcl
Debug: 14 2 configuration.c:88 find_file(): found /net/home/vaidyanathan/Projects/ibex_super_system/util/a7-ac701-openocd-cfg.tcl
Debug: 15 2 command.c:155 script_debug(): command - adapter driver ftdi
Debug: 16 2 command.c:155 script_debug(): command - transport select jtag
Debug: 17 2 command.c:155 script_debug(): command - ftdi vid_pid 0x0403 0x6010
Debug: 18 2 command.c:155 script_debug(): command - ftdi channel 0
Debug: 19 2 command.c:155 script_debug(): command - ftdi layout_init 0x0088 0x008b
Debug: 20 2 command.c:155 script_debug(): command - reset_config none
Debug: 21 2 command.c:155 script_debug(): command - jtag newtap riscv cpu -irlen 6 -ignore-version -expected-id 0x13636093
Debug: 22 2 tcl.c:557 jim_newtap_cmd(): Creating New Tap, Chip: riscv, Tap: cpu, Dotted: riscv.cpu, 5 params
Debug: 23 2 tcl.c:582 jim_newtap_cmd(): Processing option: -irlen
Debug: 24 2 tcl.c:582 jim_newtap_cmd(): Processing option: -ignore-version
Debug: 25 2 tcl.c:582 jim_newtap_cmd(): Processing option: -expected-id
Debug: 26 2 core.c:1474 jtag_tap_init(): Created Tap: riscv.cpu @ abs position 0, irlen 6, capture: 0x1 mask: 0x3
Debug: 27 2 command.c:155 script_debug(): command - target create riscv.cpu riscv -chain-position riscv.cpu
Debug: 28 2 target.c:2199 target_free_all_working_areas_restore(): freeing all working areas
Debug: 29 2 riscv.c:427 riscv_create_target(): riscv_create_target()
Debug: 30 2 command.c:155 script_debug(): command - riscv set_ir idcode 0x09
Debug: 31 2 command.c:155 script_debug(): command - riscv set_ir dtmcs 0x22
Debug: 32 2 command.c:155 script_debug(): command - riscv set_ir dmi 0x23
Debug: 33 2 command.c:155 script_debug(): command - adapter speed 10000
Debug: 34 2 adapter.c:251 adapter_config_khz(): handle adapter khz
Debug: 35 2 adapter.c:215 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 36 2 adapter.c:215 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 37 2 command.c:155 script_debug(): command - riscv set_prefer_sba on
Warn : 38 2 riscv.c:2373 riscv_set_prefer_sba(): `riscv set_prefer_sba` is deprecated. Please use `riscv set_mem_access` instead.
Debug: 39 3 command.c:155 script_debug(): command - gdb_report_data_abort enable
Debug: 40 3 command.c:155 script_debug(): command - gdb_report_register_access_error enable
Debug: 41 3 command.c:155 script_debug(): command - gdb_breakpoint_override hard
User : 42 3 gdb_server.c:3962 handle_gdb_breakpoint_override_command(): force hard breakpoints
Debug: 43 3 command.c:155 script_debug(): command - reset_config none
Debug: 44 3 command.c:155 script_debug(): command - init
Debug: 45 3 command.c:155 script_debug(): command - target init
Debug: 46 3 command.c:155 script_debug(): command - target names
Debug: 47 3 command.c:155 script_debug(): command - riscv.cpu cget -event gdb-flash-erase-start
Debug: 48 3 command.c:155 script_debug(): command - riscv.cpu configure -event gdb-flash-erase-start reset init
Debug: 49 3 command.c:155 script_debug(): command - riscv.cpu cget -event gdb-flash-write-end
Debug: 50 3 command.c:155 script_debug(): command - riscv.cpu configure -event gdb-flash-write-end reset halt
Debug: 51 3 command.c:155 script_debug(): command - riscv.cpu cget -event gdb-attach
Debug: 52 3 command.c:155 script_debug(): command - riscv.cpu configure -event gdb-attach halt 1000
Debug: 53 3 target.c:1657 handle_target_init_command(): Initializing targets...
Debug: 54 3 riscv.c:440 riscv_init_target(): riscv_init_target()
Debug: 55 3 semihosting_common.c:109 semihosting_common_init():
Debug: 56 3 ftdi.c:654 ftdi_initialize(): ftdi interface using shortest path jtag state transitions
Debug: 57 12 mpsse.c:412 mpsse_purge(): -
Debug: 58 16 mpsse.c:693 mpsse_loopback_config(): off
Debug: 59 16 mpsse.c:738 mpsse_set_frequency(): target 10000000 Hz
Debug: 60 16 mpsse.c:730 mpsse_rtck_config(): off
Debug: 61 16 mpsse.c:719 mpsse_divide_by_5_config(): off
Debug: 62 16 mpsse.c:699 mpsse_set_divisor(): 2
Debug: 63 16 mpsse.c:762 mpsse_set_frequency(): actually 10000000 Hz
Debug: 64 16 adapter.c:215 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 65 16 adapter.c:219 adapter_khz_to_speed(): have adapter set up
Debug: 66 16 mpsse.c:738 mpsse_set_frequency(): target 10000000 Hz
Debug: 67 16 mpsse.c:730 mpsse_rtck_config(): off
Debug: 68 16 mpsse.c:719 mpsse_divide_by_5_config(): off
Debug: 69 16 mpsse.c:699 mpsse_set_divisor(): 2
Debug: 70 16 mpsse.c:762 mpsse_set_frequency(): actually 10000000 Hz
Info : 71 16 ftdi.c:279 ftdi_speed(): ftdi: if you experience problems at higher adapter clocks, try the command "ftdi tdo_sample_edge falling"
Debug: 72 16 adapter.c:215 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 73 16 adapter.c:219 adapter_khz_to_speed(): have adapter set up
Info : 74 16 adapter.c:179 adapter_init(): clock speed 10000 kHz
Debug: 75 16 openocd.c:150 handle_init_command(): Debug Adapter init complete
Debug: 76 16 command.c:155 script_debug(): command - transport init
Debug: 77 16 transport.c:219 handle_transport_init(): handle_transport_init
Debug: 78 16 core.c:830 jtag_add_reset(): SRST line released
Debug: 79 16 core.c:855 jtag_add_reset(): TRST line released
Debug: 80 16 core.c:328 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 81 16 command.c:155 script_debug(): command - jtag arp_init
Debug: 82 16 core.c:1509 jtag_init_inner(): Init JTAG chain
Debug: 83 16 core.c:328 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 84 16 core.c:1234 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS
Debug: 85 16 core.c:328 jtag_call_event_callbacks(): jtag event: TAP reset
Info : 86 16 core.c:1133 jtag_examine_chain_display(): JTAG tap: riscv.cpu tap/device found: 0x13636093 (mfg: 0x049 (Xilinx), part: 0x3636, ver: 0x1)
Debug: 87 16 core.c:1364 jtag_validate_ircapture(): IR capture validation scan
Debug: 88 16 core.c:1421 jtag_validate_ircapture(): riscv.cpu: IR capture 0x35
Debug: 89 16 command.c:155 script_debug(): command - dap init
Debug: 90 16 arm_dap.c:97 dap_init_all(): Initializing all DAPs ...
Debug: 91 16 openocd.c:167 handle_init_command(): Examining targets...
Debug: 92 16 target.c:1843 target_call_event_callbacks(): target event 19 (examine-start) for core riscv.cpu
Debug: 93 16 riscv.c:1120 riscv_examine(): riscv_examine()
Debug: 94 16 riscv.c:401 dtmcontrol_scan(): DTMCONTROL: 0x0 -> 0x1071
Debug: 95 16 riscv.c:1130 riscv_examine(): dtmcontrol=0x1071
Debug: 96 16 riscv.c:1132 riscv_examine(): version=0x1
Debug: 97 16 riscv-013.c:2281 init_target(): init
Debug: 98 16 riscv-013.c:451 dtmcontrol_scan(): DTMCS: 0x0 -> 0x1071
Debug: 99 16 riscv-013.c:1571 examine(): dtmcontrol=0x1071
Debug: 100 16 riscv-013.c:1572 examine(): dmireset=0
Debug: 101 16 riscv-013.c:1573 examine(): idle=1
Debug: 102 16 riscv-013.c:1574 examine(): dmistat=0
Debug: 103 16 riscv-013.c:1575 examine(): abits=7
Debug: 104 16 riscv-013.c:1576 examine(): version=1
Debug: 105 16 riscv-013.c:257 get_dm(): [0] Allocating new DM
Debug: 106 17 riscv-013.c:397 scan(): 41b w 00000000 @10 -> + 00000000 @00; 0i
Debug: 107 17 riscv-013.c:397 scan(): 41b - 00000000 @10 -> + 00000000 @10; 0i
Debug: 108 17 riscv-013.c:397 scan(): 41b w 00000001 @10 -> b 00000000 @10; 0i
Debug: 109 17 riscv-013.c:407 scan(): dmactive ->
Debug: 110 17 riscv-013.c:460 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=1, ac_busy_delay=0
Debug: 111 17 riscv-013.c:451 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 112 17 riscv-013.c:397 scan(): 41b w 00000001 @10 -> + 00000000 @10; 1i
Debug: 113 17 riscv-013.c:407 scan(): dmactive ->
Debug: 114 17 riscv-013.c:397 scan(): 41b - 00000000 @10 -> b 00000000 @10; 1i
Debug: 115 17 riscv-013.c:460 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=2, ac_busy_delay=0
Debug: 116 17 riscv-013.c:451 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 117 17 riscv-013.c:397 scan(): 41b - 00000000 @10 -> + 00000000 @10; 2i
Debug: 118 17 riscv-013.c:397 scan(): 41b w 07ffffc1 @10 -> b 00000000 @10; 2i
Debug: 119 17 riscv-013.c:407 scan(): hasel hartselhi=1023 hartsello=1023 dmactive ->
Debug: 120 17 riscv-013.c:460 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=3, ac_busy_delay=0
Debug: 121 17 riscv-013.c:451 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 122 17 riscv-013.c:397 scan(): 41b w 07ffffc1 @10 -> + 00000000 @10; 3i
Debug: 123 17 riscv-013.c:407 scan(): hasel hartselhi=1023 hartsello=1023 dmactive ->
Debug: 124 17 riscv-013.c:397 scan(): 41b - 00000000 @10 -> b 00000000 @10; 3i
Debug: 125 17 riscv-013.c:460 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=4, ac_busy_delay=0
Debug: 126 17 riscv-013.c:451 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 127 17 riscv-013.c:397 scan(): 41b - 00000000 @10 -> + 00000000 @10; 4i
Debug: 128 17 riscv-013.c:397 scan(): 41b r 00000000 @10 -> b 00000000 @10; 4i
Debug: 129 17 riscv-013.c:460 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=5, ac_busy_delay=0
Debug: 130 17 riscv-013.c:451 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 131 17 riscv-013.c:397 scan(): 41b r 00000000 @10 -> + 00000000 @10; 5i
Debug: 132 17 riscv-013.c:397 scan(): 41b - 00000000 @10 -> b 00000000 @10; 5i
Debug: 133 17 riscv-013.c:460 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=6, ac_busy_delay=0
Debug: 134 18 riscv-013.c:451 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 135 18 riscv-013.c:397 scan(): 41b - 00000000 @10 -> + 00000000 @10; 6i
Error: 136 18 riscv-013.c:1611 examine(): Debug Module did not become active. dmcontrol=0x0
Debug: 137 18 target.c:1843 target_call_event_callbacks(): target event 20 (examine-fail) for core riscv.cpu
Warn : 138 18 target.c:802 target_examine(): target riscv.cpu examination failed
Debug: 139 18 openocd.c:169 handle_init_command(): target examination failed
Debug: 140 18 command.c:155 script_debug(): command - flash init
Debug: 141 18 tcl.c:1375 handle_flash_init_command(): Initializing flash devices...
Debug: 142 18 command.c:155 script_debug(): command - nand init
Debug: 143 18 tcl.c:487 handle_nand_init_command(): Initializing NAND devices...
Debug: 144 18 command.c:155 script_debug(): command - pld init
Debug: 145 18 pld.c:194 handle_pld_init_command(): Initializing PLDs...
Debug: 146 18 command.c:155 script_debug(): command - tpiu init
Info : 147 18 gdb_server.c:3791 gdb_target_start(): starting gdb server for riscv.cpu on 3333
Info : 148 18 server.c:297 add_service(): Listening on port 3333 for gdb connections
Debug: 149 18 command.c:155 script_debug(): command - halt
Debug: 150 18 target.c:3305 handle_halt_command(): -
Error: 151 18 target.c:590 target_halt(): Target not examined yet
Debug: 152 18 command.c:544 run_command(): Command 'halt' failed with error code -4
User : 153 18 command.c:608 command_run_line():
Debug: 154 18 riscv.c:489 riscv_deinit_target(): riscv_deinit_target()
Debug: 155 18 riscv-013.c:1526 deinit_target(): riscv_deinit_target()
Debug: 156 18 target.c:2199 target_free_all_working_areas_restore(): freeing all working areas
Here is my slightly modified OpenOCD tcl config:
adapter driver ftdi
transport select jtag
ftdi vid_pid 0x0403 0x6010
ftdi channel 0
ftdi layout_init 0x0088 0x008b
reset_config none
# Configure JTAG chain and the target processor
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 6 -ignore-version -expected-id 0x13636093
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
riscv set_ir idcode 0x09
riscv set_ir dtmcs 0x22
riscv set_ir dmi 0x23
adapter speed 10000
riscv set_prefer_sba on
gdb_report_data_abort enable
gdb_report_register_access_error enable
gdb_breakpoint_override hard
reset_config none
init
haltI am unable to understand why this error is being caused: Debug Module did not become active. dmcontrol=0x0.
To my understanding the IR register mapping should remain the same, since I am using the same Xilinx BSCANE2 based JTAG implementation and FPGA. I have also tried lowering the design clock from 50MHz to 10 MHz to no avail. Kindly let me know what I could look into to understand and fix this issue.
Thanks in advance,
Arun
Changing Ibex core configuration parameters for synthesis
If there a convenient way to change the Ibex core configuration parameters for synthesis (for example, to change the multiplier implementation to RV32MSingleCycle)? I experimented a bit with the build options and I didn't find a way to set those parameters externally in a way that Vivado would respect. Of course changing the parameters directly in the rtl works fine, e.g.:
--- a/vendor/lowrisc_ibex/rtl/ibex_top.sv
+++ b/vendor/lowrisc_ibex/rtl/ibex_top.sv
@@ -13,19 +13,19 @@
* Top level module of the ibex RISC-V core
*/
module ibex_top import ibex_pkg::*; #(
- parameter bit PMPEnable = 1'b0,
+ parameter bit PMPEnable = 1'b1,
parameter int unsigned PMPGranularity = 0,
... but is there a better way to do it? Sorry for the beginner question, I am a newbie with Vivado and related tools.
multicore support
Does it support multicore?
JTAG interface
I want to test the project on a ZedBoard. How can work if the JTAG signals are all 0? where is defined DMIDirectTAP? How can I modify the code making JTAG external?
FuseSoc program not working
At the moment the FuseSoC command to program the FPGA is not working on my setup:
Line 67 in 3ae1363
I just says INFO: Running, but then does nothing.
I am still able to program my FPGA using Vivado.
Cadence verilog compiler doesn't seem to like the parameter declared after usage
Cadence verilog compiler causes the following error
file: /tst/ibex_soc/data/ibex_soc_lib/ibex_super_system/rtl/system/dm_top.sv
input logic [BusWidth-1:0] slave_addr_i,
|
xmvlog: *E,UNDIDN (/tst/ibex_soc/data/ibex_soc_lib/ibex_super_system/rtl/system/dm_top.sv,32|23): 'BusWidth': undeclared identifier [12.5(IEEE)].
input logic [BusWidth/8-1:0] slave_be_i,
|
xmvlog: *E,UNDIDN (/tst/ibex_soc/data/ibex_soc_lib/ibex_super_system/rtl/system/dm_top.sv,33|23): 'BusWidth': undeclared identifier [12.5(IEEE)].
input logic [BusWidth-1:0] slave_wdata_i,
|
xmvlog: *E,UNDIDN (/tst/ibex_soc/data/ibex_soc_lib/ibex_super_system/rtl/system/dm_top.sv,34|23): 'BusWidth': undeclared identifier [12.5(IEEE)].
output logic [BusWidth-1:0] slave_rdata_o,
|
xmvlog: *E,UNDIDN (/tst/ibex_soc/data/ibex_soc_lib/ibex_super_system/rtl/system/dm_top.sv,35|23): 'BusWidth': undeclared identifier [12.5(IEEE)].
output logic [BusWidth-1:0] master_add_o,
|
xmvlog: *E,UNDIDN (/tst/ibex_soc/data/ibex_soc_lib/ibex_super_system/rtl/system/dm_top.sv,39|23): 'BusWidth': undeclared identifier [12.5(IEEE)].
output logic [BusWidth-1:0] master_wdata_o,
|
xmvlog: *E,UNDIDN (/tst/ibex_soc/data/ibex_soc_lib/ibex_super_system/rtl/system/dm_top.sv,41|23): 'BusWidth': undeclared identifier [12.5(IEEE)].
output logic [BusWidth/8-1:0] master_be_o,
|
xmvlog: *E,UNDIDN (/tst/ibex_soc/data/ibex_soc_lib/ibex_super_system/rtl/system/dm_top.sv,42|23): 'BusWidth': undeclared identifier [12.5(IEEE)].
input logic [BusWidth-1:0] master_r_rdata_i
|
xmvlog: *E,UNDIDN (/tst/ibex_soc/data/ibex_soc_lib/ibex_super_system/rtl/system/dm_top.sv,45|23): 'BusWidth': undeclared identifier [12.5(IEEE)].
The following seems to fix it
diff --git a/rtl/system/dm_top.sv b/rtl/system/dm_top.sv
index 23e3ce6..4d26daa 100644
--- a/rtl/system/dm_top.sv
+++ b/rtl/system/dm_top.sv
@@ -14,7 +14,8 @@
module dm_top #(
parameter int NrHarts = 1,
- parameter logic [31:0] IdcodeValue = 32'h 0000_0001
+ parameter logic [31:0] IdcodeValue = 32'h 0000_0001,
+ parameter int BusWidth = 32
) (
input logic clk_i, // clock
input logic rst_ni, // asynchronous reset active low, connect PoR
@@ -47,7 +48,7 @@ module dm_top #(
`ASSERT_INIT(paramCheckNrHarts, NrHarts > 0)
- localparam int BusWidth = 32;
+// localparam int BusWidth = 32;
// all harts have contiguous IDs
localparam logic [NrHarts-1:0] SelectableHarts = {NrHarts{1'b1}};
Recommend Projects
-
React
A declarative, efficient, and flexible JavaScript library for building user interfaces.
-
Vue.js
🖖 Vue.js is a progressive, incrementally-adoptable JavaScript framework for building UI on the web.
-
Typescript
TypeScript is a superset of JavaScript that compiles to clean JavaScript output.
-
TensorFlow
An Open Source Machine Learning Framework for Everyone
-
Django
The Web framework for perfectionists with deadlines.
-
Laravel
A PHP framework for web artisans
-
D3
Bring data to life with SVG, Canvas and HTML. 📊📈🎉
-
Recommend Topics
-
javascript
JavaScript (JS) is a lightweight interpreted programming language with first-class functions.
-
web
Some thing interesting about web. New door for the world.
-
server
A server is a program made to process requests and deliver data to clients.
-
Machine learning
Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.
-
Visualization
Some thing interesting about visualization, use data art
-
Game
Some thing interesting about game, make everyone happy.
Recommend Org
-
Facebook
We are working to build community through open source technology. NB: members must have two-factor auth.
-
Microsoft
Open source projects and samples from Microsoft.
-
Google
Google ❤️ Open Source for everyone.
-
Alibaba
Alibaba Open Source for everyone
-
D3
Data-Driven Documents codes.
-
Tencent
China tencent open source team.