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40gbe

A 40GBE optical network tester

across

Across the Great Wall we can reach every corner in the world

ahb2apb

ahb3lite_dma

DMA core compatible with AHB3-Lite

ahb3lite_interconnect

AHB3-Lite Interconnect

ahb_lite_uart16550

UART 16550 core for MIPSfpga+ system

ahblite2apb

AHBLite bus to APB4 bridge

allarbiterrtlcode

RTL code of some arbitration algorithm

android_kernel_vernee_apollo_lite

Kernel Source for Vernee Apollo Lite & X

apb_can

CAN controller for APB interface

appleriscv

A RISCV CPU written in Spinalhdl.

arm_cortex-m3

该项目依据全国大学生集成电路创新创业大赛“ARM杯”赛题要求，在FPGA上搭建Cortex-M3软核、图像协处理器，并通过OV5640摄像头采集车牌图像，实现对车牌的识别与结果显示。项目基于Altera DE1 FPGA搭载Cortex-M3软核，依据AHB-Lite总线协议，将LCD1602、RAM、图像协处理器等外设挂载至Cortex-M3。视频采集端，设计写FiFo模块、SDRAM存储与输出、读FiFo模块、灰度处理模块、二值化、VGA显示等模块。最终将400位宽的结果数据（对应20张车牌）存储在RAM中，输出至AHB总线，由Cortex-M3调用并显示识别结果。

arm_m3_design

personal practice

asyn_fifo

异步fifo模块

async-fifo

Asynchronous FIFO for transferring data between two asynchronous clock domains

async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

asynchronous-fifo

Asynchronous fifo in verilog

axi-dma

axi-lite-master-interface

use verilog to config IP with axi-lite interface

axi_cache

verification of simple axi-based cache

axis-async-fifo

parameterized AXIS FIFO design

baota

宝塔面板docker部署

bj-unicom-iptv

[DEPRECATED]Beijing Unicom IPTV playlist. Deprecated, use these instead: https://gist.github.com/sdhzdmzzl/93cf74947770066743fff7c7f4fc5820 https://github.com/wuwentao/bj-unicom-iptv

bj-unicom-iptv-scanner

iptv channel scanner

cdc_fifo_design

Multi-bit Synchronization across Clock Domains

centos-dxf

chainsaw

chainsaw-1

a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communication and Crypto applications

chips-demo-ethernet_mac

ethernet_mac Demo with Chips-2.0 HTTP server on GigaBee

chipspp

C/C++-to-Verilog ASIP generator.