hst10 / pylog Goto Github PK

Parent issue: #1

An empty init.py marks its directory as a module.

I propose the code to be restructured into

Readme.md

......
pylog/optimizer.py
pylog/pylog.py
tests/......
......

In pylog/pylog.py, optimizer.py can be now imported by absolute import statement

import pylog.optimizer

This enhancement much clarifies the import statements.

https://github.com/UCLA-VAST/soda is an example.

Code in python as follows

                if (len>4):
                    limit=3
                elif (len>2):
                    limit=2
                elif (len==2):
                    limit=1
                else:
                    limit=0

generates

if (len > 4)
      {
        int limit = 3;
      }
      else
      {
        if (len > 2)
        {
          limit = 2;
        }
        else
        {
          if (len == 2)
          {
            limit = 1;
          }
          else
          {
            limit = 0;
          }

        }

      }

in C. Should be

int limit 
if (len > 4)
      {
        limit = 3;
      }
      else
      {
        if (len > 2)
        {
          limit = 2;
        }
        else
        {
          if (len == 2)
          {
            limit = 1;
          }
          else
          {
            limit = 0;
          }

        }

      }

pynq-z2 is the ECE527-class-use-board. Supporting this can also help me get familiar with the sysgen code base.

1. Materials

• writing jinja2 template for pynq-z2 board
  https://www.kite.com/python/docs/jinja2.FileSystemLoader

This issue is supposed to be an aggregate list of the TODOs in code clean up efforts (not prioritized at this moment but we might want to work on this some time in the future). In the meantime, please feel free to reply to this thread (if you can't modify it) to add items you deem necessary.

1. Separate path and other environment variables to an individual configuration file. Developers are expected to not commit it when they make modification to it during local development.

   • including the TEMPLATE_DIR variable in sysgen.py

2. Add .gitignore

3. Add a style linter configuration file into the project to govern the style automated check.

   • limit all lines in code to a maximum of 79 characters, as suggested by PEP 8.

4. There seem to be redundant new line after every for loop in the generated C code. Remove them in the compiler logic if there are.

1. Related materials

• see example code:
  https://github.com/Xilinx/Vitis_Accel_Examples/blob/f72dff9eea45a76e9ee0713774589624e2b52c9f/sys_opt/slr_assign/Makefile#L89

• Vitis doc, page 323
  ug1393-vitis-application-acceleration.pdf
  https://www.xilinx.com/cgi-bin/docs/rdoc?v=2020.1;d=ug1399-vitis-hls.pdf

• host code modification
  https://xilinx.github.io/Vitis_Accel_Examples/master/html/mult_compute_units.html

• host side for xrt:
  https://pynq.readthedocs.io/en/v2.5.1/pynq_alveo.html

• host side for soc:
  https://pynq.readthedocs.io/en/v2.1/pynq_libraries.html

2. Sub tasks

• needs memory bank partition
• adding new decorator in pylog
• task partition apply ? independent testing
• extend sysgen commands to file-level script

Parent issue: #1
TODO list:
177f84f

Eg: The bare code for matmul.py is not compatible with python anymore. (

Hi @hst10 , may i know ur pylot support one tranied NN model from pytorch to hls code process for U200 board？ if yes, how to set up this env. thanks