Comments (3)
Instead of defining PCM_TEST_FALLBACK_TO_ATOM changed RPL value to 170, now it works even without PCM_NO_PERF
===== Processor information =====
Linux arch_perfmon flag : yes
Hybrid processor : yes
IBRS and IBPB supported : yes
STIBP supported : yes
Spec arch caps supported : yes
Max CPUID level : 35
CPU model number : 170
Number of logical cores: 22
Number of online logical cores: 22
Threads (logical cores) per physical core: 15 (maybe imprecise due to core offlining/hybrid CPU)
Offlined cores:
Num sockets: 1
Physical cores per socket: 1 (maybe imprecise due to core offlining/hybrid CPU)
Core PMU (perfmon) version: 5
Number of core PMU generic (programmable) counters: 8
Width of generic (programmable) counters: 48 bits
Number of core PMU fixed counters: 3
Width of fixed counters: 48 bits
Nominal core frequency: 3000000000 Hz
IBRS enabled in the kernel : no
STIBP enabled in the kernel : no
The processor is not susceptible to Rogue Data Cache Load: yes
The processor supports enhanced IBRS : yes
Package thermal spec power: 28 Watt; Package minimum power: 0 Watt; Package maximum power: 0 Watt;
INFO: Linux perf interface to program uncore PMUs is present
Socket 0: 0 PCU units detected. 0 IIO units detected. 0 IRP units detected. 0 CHA/CBO units detected. 0 MDF units detected. 0 UBOX units detected. 0 CXL units detected.
Closed perf event handles
Trying to use Linux perf events...
Linux kernel perf rejects an architectural event on your platform. Using direct PMU programming instead.
Detected Intel(R) Core(TM) Ultra 7 155H "Intel(r) microarchitecture codename Raptor Lake" stepping 4 microcode level 0x1c
UTIL : utlization (same as core C0 state active state residency, the value is in 0..1)
IPC : instructions per CPU cycle
CFREQ : core frequency in Ghz
L3MISS: L3 (read) cache misses
L2MISS: L2 (read) cache misses (including other core's L2 cache *hits*)
L3HIT : L3 (read) cache hit ratio (0.00-1.00)
L2HIT : L2 cache hit ratio (0.00-1.00)
L3MPI : number of L3 (read) cache misses per instruction
L2MPI : number of L2 (read) cache misses per instruction
READ : bytes read from main memory controller (in GBytes)
WRITE : bytes written to main memory controller (in GBytes)
TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature
energy: Energy in Joules
Core (SKT) | UTIL | IPC | CFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3MPI | L2MPI | TEMP
0 0 0.05 1.18 1.47 919 K 128 K 0.45 0.72 0.0109 0.0015 66
1 0 0.00 0.15 1.93 12 K 2687 0.67 0.65 0.0173 0.0039 66
2 0 0.01 0.46 1.88 200 K 38 K 0.78 0.45 0.0225 0.0043 67
3 0 0.00 0.25 2.00 8362 1471 0.75 0.47 0.0391 0.0069 67
4 0 0.01 0.83 1.71 184 K 37 K 0.70 0.51 0.0106 0.0021 67
5 0 0.05 1.40 1.41 951 K 258 K 0.52 0.76 0.0102 0.0028 67
6 0 0.01 0.32 1.94 84 K 20 K 0.82 0.39 0.0243 0.0058 67
7 0 0.00 0.19 1.95 77 K 8905 0.70 0.32 0.0849 0.0097 67
8 0 0.03 1.05 1.47 529 K 93 K 0.60 0.72 0.0134 0.0024 66
9 0 0.00 0.26 1.92 612 385 0.86 0.32 0.0165 0.0104 66
10 0 0.01 0.41 1.76 266 K 40 K 0.70 0.56 0.0290 0.0044 66
11 0 0.00 0.31 1.66 15 K 4808 0.79 0.28 0.0358 0.0108 66
12 0 0.01 0.44 1.66 101 K 1676 0.72 0.95 0.0219 0.0004 66
13 0 0.01 0.28 1.64 255 K 3341 0.70 0.94 0.0380 0.0005 66
14 0 0.02 0.72 1.72 297 K 2394 0.59 0.98 0.0140 0.0001 66
15 0 0.01 0.45 1.64 115 K 2494 0.69 0.94 0.0201 0.0004 66
16 0 0.01 0.52 1.45 71 K 2904 0.70 0.95 0.0171 0.0007 65
17 0 0.00 0.31 1.42 37 K 1710 0.89 0.90 0.0207 0.0009 65
18 0 0.00 0.37 1.42 25 K 2372 0.88 0.89 0.0125 0.0012 65
19 0 0.02 1.03 1.73 297 K 2380 0.50 0.97 0.0109 0.0001 65
20 0 0.00 0.20 1.10 5371 2 0.47 0.99 0.1896 0.0001 63
21 0 0.00 0.27 1.10 2779 3 0.70 0.99 0.0764 0.0001 63
---------------------------------------------------------------------------------------------------------------
SKT 0 0.01 0.86 1.58 4460 K 654 K 0.63 0.75 0.0134 0.0020 61
---------------------------------------------------------------------------------------------------------------
TOTAL * 0.01 0.86 1.58 4460 K 654 K 0.63 0.75 0.0134 0.0020 N/A
Instructions retired: 332 M ; Active cycles: 385 M ; Time (TSC): 2996 Mticks ; C0 (active,non-halted) core residency: 1.11 %
C1 core residency: 8.56 %; C3 core residency: 0.00 %; C6 core residency: 44.84 %; C7 core residency: 45.49 %;
C0 package residency: 100.00 %; C2 package residency: 0.00 %; C4 package residency: 0.00 %; C6 package residency: 0.00 %;
┌────────────────────────────────────────────────────────────────────────────────┐
Core C-state distribution│01111111666666666666666666666666666666666666777777777777777777777777777777777777│
└────────────────────────────────────────────────────────────────────────────────┘
┌────────────────────────────────────────────────────────────────────────────────┐
Package C-state distribution│00000000000000000000000000000000000000000000000000000000000000000000000000000000│
└────────────────────────────────────────────────────────────────────────────────┘
---------------------------------------------------------------------------------------------------------------
MEM (GB)->| READ | WRITE | CPU energy | PP0 energy | PP1 energy |
---------------------------------------------------------------------------------------------------------------
SKT 0 0.49 0.13 4.89 1.42 0.02
---------------------------------------------------------------------------------------------------------------
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thanks for reporting and finding the workaround. We will add native support for this cpu model soon
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If defining PCM_TEST_FALLBACK_TO_ATOM
...
Fall back to ATOM functionality.
Number of logical cores: 22
Number of online logical cores: 22
Threads (logical cores) per physical core: 15 (maybe imprecise due to core offlining/hybrid CPU)
Offlined cores:
Num sockets: 1
Physical cores per socket: 1 (maybe imprecise due to core offlining/hybrid CPU)
Core PMU (perfmon) version: 5
Number of core PMU generic (programmable) counters: 8
Width of generic (programmable) counters: 48 bits
Number of core PMU fixed counters: 3
Width of fixed counters: 48 bits
Nominal core frequency: 3000000000 Hz
IBRS enabled in the kernel : no
STIBP enabled in the kernel : no
The processor is not susceptible to Rogue Data Cache Load: yes
The processor supports enhanced IBRS : yes
INFO: Linux perf interface to program uncore PMUs is present
Socket 0: 0 PCU units detected. 0 IIO units detected. 0 IRP units detected. 0 CHA/CBO units detected. 0 MDF units detected. 0 UBOX units detected. 0 CXL units detected.
Closed perf event handles
Trying to use Linux perf events...
Linux Perf: Error when programming generic event #0 on core #13, error: No such file or directory with config 0x8000000000430000 config1 0x0 for tid -1 leader 39
try running with environment variable PCM_NO_PERF=1
Linux Perf: Error when programming generic event #0 on core #16, error: No such file or directory with config 0x8000000000430000 config1 0x0 for tid -1 leader 43
try running with environment variable PCM_NO_PERF=1
Linux Perf: Error when programming generic event #0 on core #19, error: No such file or directory with config 0x8000000000430000 config1 0x0 for tid -1 leader 45
try running with environment variable PCM_NO_PERF=1
Linux Perf: Error when programming generic event #0 on core #17, error: No such file or directory with config 0x8000000000430000 config1 0x0 for tid -1 leader 33
try running with environment variable PCM_NO_PERF=1
Linux Perf: Error when programming generic event #0 on core #12, error: No such file or directory with config 0x8000000000430000 config1 0x0 for tid -1 leader 36
try running with environment variable PCM_NO_PERF=1
Linux Perf: Error when programming generic event #0 on core #14, error: No such file or directory with config 0x8000000000430000 config1 0x0 for tid -1 leader 42
try running with environment variable PCM_NO_PERF=1
Linux Perf: Error when programming generic event #0 on core #15, error: No such file or directory with config 0x8000000000430000 config1 0x0 for tid -1 leader 41
try running with environment variable PCM_NO_PERF=1
Linux Perf: Error when programming generic event #0 on core #21, error: No such file or directory with config 0x8000000000430000 config1 0x0 for tid -1 leader 44
try running with environment variable PCM_NO_PERF=1
Linux Perf: Error when programming generic event #0 on core #20, error: No such file or directory with config 0x8000000000430000 config1 0x0 for tid -1 leader 40
try running with environment variable PCM_NO_PERF=1
Linux Perf: Error when programming generic event #0 on core #18, error: No such file or directory with config 0x8000000000430000 config1 0x0 for tid -1 leader 31
try running with environment variable PCM_NO_PERF=1
Access to Intel(r) Performance Counter Monitor has denied (Unknown error).
Cleaning up
Closed perf event handles
Zeroed uncore PMU registers
Setting PCM_NO_PERF=1 then leads to normal(?) output
Usage of Linux perf events is disabled through PCM_NO_PERF environment variable. Using direct PMU programming...
Detected Intel(R) Core(TM) Ultra 7 155H "Intel(r) microarchitecture codename Atom(tm)" stepping 4 microcode level 0x1c
UTIL : utlization (same as core C0 state active state residency, the value is in 0..1)
IPC : instructions per CPU cycle
L2MISS: L2 (read) cache misses
L2HIT : L2 cache hit ratio (0.00-1.00)
L2MPI : number of L2 (read) cache misses per instruction
TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature
energy: Energy in Joules
Core (SKT) | UTIL | IPC | L2MISS | L2HIT | L2MPI | TEMP
0 0 0.05 0.64 761 K 0.65 0.0147 72
1 0 0.00 0.12 12 K 0.63 0.0288 72
2 0 0.03 1.07 408 K 0.78 0.0070 73
3 0 0.00 0.28 45 K 0.78 0.0454 73
4 0 0.03 1.21 304 K 0.79 0.0052 73
5 0 0.01 0.50 40 K 0.94 0.0051 73
6 0 0.01 0.45 194 K 0.86 0.0169 73
7 0 0.00 0.33 59 K 0.90 0.0225 73
8 0 0.03 0.88 264 K 0.89 0.0053 73
9 0 0.00 0.23 3034 0.87 0.0262 73
10 0 0.02 1.25 152 K 0.85 0.0034 72
11 0 0.00 0.17 2458 0.92 0.0192 72
12 0 0.03 0.49 0 0.00 0.0000 71
13 0 0.02 0.23 0 0.00 0.0000 71
14 0 0.08 0.48 0 0.00 0.0000 71
15 0 0.02 0.43 0 0.00 0.0000 71
16 0 0.00 0.29 0 0.00 0.0000 72
17 0 0.00 0.30 0 0.00 0.0000 72
18 0 0.00 0.27 0 0.00 0.0000 72
19 0 0.00 0.34 0 0.00 0.0000 72
20 0 0.00 0.14 0 0.00 0.0000 69
21 0 0.00 0.21 0 0.00 0.0000 69
---------------------------------------------------------------------------------------------------------------
TOTAL * 0.02 0.67 2248 K 0.81 0.0055 N/A
Instructions retired: 411 M ; Active cycles: 614 M ; Time (TSC): 3001 Mticks ; C0 (active,non-halted) core residency: 1.54 %
C1 core residency: 98.46 %;
C0 package residency: 100.00 %; C2 package residency: 0.00 %; C4 package residency: 0.00 %; C6 package residency: 0.00 %;
┌────────────────────────────────────────────────────────────────────────────────┐
Core C-state distribution│01111111111111111111111111111111111111111111111111111111111111111111111111111111│
└────────────────────────────────────────────────────────────────────────────────┘
┌────────────────────────────────────────────────────────────────────────────────┐
Package C-state distribution│00000000000000000000000000000000000000000000000000000000000000000000000000000000│
└────────────────────────────────────────────────────────────────────────────────┘
---------------------------------------------------------------------------------------------------------------
MEM (GB)->|
---------------------------------------------------------------------------------------------------------------
SKT 0
---------------------------------------------------------------------------------------------------------------
My system is running Ubuntu 24.04 with CachyOS kernel 6.8.1, just in case.
from pcm.
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