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Name: Jayesh Patil
Type: User
Name: Jayesh Patil
Type: User
Optimizing a resistor value for a passive-balancing design to minimize instantaneous heat generated Optimize a resistor value for a passive-balancing design to minimize balancing time Generalize HPPC method to account for SOC and temperature-varying design limits Generalize HPPC method to allow SOC-varying discharge and charge resistances
To set up and run a vehicle/battery co-simulation and to visualize results.
The data is collected from an actual cell in the laboratory. At the beginning of the test, the cell was resting at a high state of charge. The test rested for 5 minutes and then a constant-current discharge pulse was applied for 15 minutes. The cell was then allowed to rest for one hour. Voltage and current were measured every second.
Optimize tuning values for an EKF to minimize SOC estimation error Optimize tuning values for an EKF to minimize error bounds while simultaneously ensuring errors are within bounds Optimize tuning values for an SPKF to minimize SOC estimation error Optimize tuning values for an SPKF to minimize error bounds while simultaneously ensuring errors are within bounds
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