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jeffreyyunz's Projects

altera-makefile icon altera-makefile

Allows commandline builds, and project creation for Altera's Quartus II

cordic icon cordic

An implementation of the CORDIC algorithm in Verilog.

cores icon cores

Various HDL (Verilog) IP Cores

cpu icon cpu

A very primitive but hopefully self-educational CPU in Verilog

cpuonfpga icon cpuonfpga

It's a basic computer designed using VERILOG on XILINX FPGA architecture.

darkriscv icon darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

digital-design icon digital-design

An introduction to integrated circuit design with Verilog and the Papilio Pro development board.

dpll icon dpll

A collection of phase locked loop (PLL) related projects

ece253 icon ece253

Digital and Computer Systems (Fall 2018)

ece253-labs icon ece253-labs

Verilog and ARM Assembly labs for second year Digital and Computer Systems (ECE253) course at the University of Toronto

fpga-peripherals icon fpga-peripherals

:seedling: :snowflake: Collection of open-source peripherals in Verilog

hdl icon hdl

HDL libraries and projects

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