jeras Goto Github PK

adams

all digital PLL

axi-bfm

Automatically exported from code.google.com/p/axi-bfm

butterflylogic

ca-equivalence

brute-force rule equivalence search

cellular-automata-sage-toolkit

Automatically exported from code.google.com/p/cellular-automata-sage-toolkit

ecs8

projects related to the ECS8 board

example-systemverilog

fpga-hdl

A set of small Verilog projects, to simulate and implement on FPGA development boards

fpga_pio

An attempt to recreate the RP2040 PIO in an FPGA

fpga_synthesys_issues

Debugging FPGA synthesis issues, article and examples

fri-magisterij

LaTeX templates for theses written at Faculty of Computer and Information Science, University of Ljubljana.

hdl-crc

CRC implementation in HDL languages (VHDL, SystemVerilog)

hylocereusemonica

Red Pitaya Ecosystem and Applications

hylocereusemonica-jupyter

Python API and interactive web applications

iverilog

Icarus Verilog

ivtest

Regression test suite for Icarus Verilog.

jeras.github.io

personal "Rattus Pubis" webpage

jtag_pulp

learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V

libiio

Library for interfacing with IIO devices

modern-computer-architecture-and-organization-second-edition

Modern Computer Architecture and Organization – Second Edition, Published by Packt

ne10

An open optimized software library project for the ARM® Architecture

office

LibreOffice templates

peakrdl-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

preimages-2d

2D cellular automata preimages count&list algorithm

readthedocs-source-links

Read the Docs issue with source links demo

red-pitaya-notes

My notes on the Red Pitaya Open Source Instrument

riscof

riscv-isa-manual

RISC-V Instruction Set Manual

riscv-isa-sim

Spike, a RISC-V ISA Simulator