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amaranth

A modern hardware definition language and toolchain based on Python

amaranth-tutorial

analog-mixed-signal-simulation-and-modeling

This is my labs for the AMS simulation and modeling Training of Siemens EDA in Summer 2022, delivered by Dr. Hesham Omran.

arxivpapers

Code behind Arxiv Papers

astran

ASTRAN - Automatic Synthesis of Transistor Networks

autockt

Deep Reinforcement Learning of Analog Circuit Designs

examples

Pre-built mlpack models

extension-summarize-translate-gemini

Chrome extension to summarize and translate web pages. Uses Gemini as the backend.

hdlgen-chatgpt

HDLGen-ChatGPT, works in tandem with ChatGPT-3.5 chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project

hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

hwtlib

hardware library for hwt (= ipcore repo)

kiwi

the leading open source test case management system

lcapy-gui

A graphical user interface for symbolic circuit analysis using Lcapy

ollama

Get up and running with Llama 2, Mistral, and other large language models locally.

polyphony

Polyphony is Python based High-Level Synthesis compiler.

pygears

HW Design: A Functional Approach

pyserdes

redcase

Test case management plug-in for the Redmine

redmine_auto_watchers_from_groups

redmine_impasse

The redmine plugin for test management.

redmine_inventory_manager

Take your warehouse or office inventory on the same platform of your projects.

redmine_synchrony

Redmine Synchrony plugin makes copies of last updated issues from another redmine instance

rmp_group_watchers

spinaldoc-rtd

The sources of the online SpinalHDL doc (Japanese Translation)

standard-cell-characterization

Open Source tool to build liberty files and for Characterizing Standard Cells.

uploaddownloadfiles-django

Django code to upload and download a file from the server. Once uploaded onto the server, python code will convert all its content to upper case. It is just used to demonstrate how a file is uploaded and downloaded from a server in Django.

veriloggen

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

vpw-testbench

Verilator Python Wrapper and testbench framework

xls

XLS: Accelerated HW Synthesis