jishdas Goto Github PK

ctb_hackathon_2023

All files submitted in RISC-V CTB Hackathon 2023, a Processor Design Verification Hackathon organized by Ministry of Electronics and Information Technology

dgs_filter

Work files of the winter internship of 2023 at NCRA-TIFR

digism_2023

evm

Proteus Simulation and Implementation of Electronic Voting Machine

floydcycle_hardware

Proteus Simulation and Implementation of Floyd's Cycle Finding Algorithm to detect cycles in a blockchain

hpc_codes

All codes ran on remote cluster and login node in HPC and AI Compute continuum workshop

jishdas

Config files for my GitHub profile.

pipeacc16

16 bit 4 stage pipelined Accumulator based processor

qec_btp

QEC codes for Quantum communication

qpsk_mod

QPSK transceivers in AWGN and Rayleigh Fading channels using zero forcing and MMSE equalization methods in MATLAB_Simulink and LabVIEW

research

riscv-ctb-challenge-jishdas

riscv-ctb-challenge-JishDas created by GitHub Classroom

sdr_code

MATLAB implementations for ADALM-PLUTO SDR

verilog-ethernet

Verilog Ethernet components for FPGA implementation copy

verilog-uart

Verilog UART