Write HDL code, one module at a time about riscv-pio

[Joeyh021]

A few basic modules done: register, program counter. Started to work on instruction set and decoding, need to design ALU as part of this.

[Joeyh021]

Execution unit done, started to look at other components. Got an Async FIFO paper i can implement, shift registers shouldn't be too hard, memory components starting to come together.

[Joeyh021]

Pins mostly done, ISR done too. Need to write OSR (copy from ISR) and verify

[Joeyh021]

OSR Done and mostly verified. Tried to do fifos, is hard. Clock divider ended up being hard too so i simplified it, but that's done.