jrrk Goto Github PK

adv_dbg_if

Advanced Debug Interface

adv_debug_sys

Personal mirror for adv_debug_sys

apb_uart

ariane

Ariane is a 6-stage RISC-V CPU

ariane-ethernet

open-source Ethenet media access controller for Ariane on Genesys-2

ariane-sdk

Ariane SDK containing RISC-V tools and Buildroot

axi

AXI4 and AXI4-Lite interface definitions and testbench utilities

axi_mem_if

Simple single-port AXI memory interface

blktests

Linux kernel block layer testing framework

boolparser

Boolean expression parser and partial simplifier written in OCaml

boom-template

A template for building new projects/platforms using the BOOM core.

buildroot

Buildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at http://git.buildroot.net/buildroot/. Do not open issues or file pull requests here.

busybox

BusyBox mirror

cbzone

Port of the classic BattleZone arcade game to LowRISC

cbzone-ios

chisel-tutorial

chisel tutorial exercises and answers

cil

C Intermediate Language

common_cells

Common SV components

compcert

The CompCert C verified compiler

cooltaxtool

UK Tax Calculator & Visualiser

coreclr

This repo contains the .NET Core runtime, called CoreCLR, and the base library, called mscorlib. It includes the garbage collector, JIT compiler, base .NET data types and many low-level classes.

custom_axi_master

A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models

debian-riscv64

debug_bridge

def-parser

Design Exchange Format (DEF) parser toolkit copy. Cadence open-source parsers for DEF

dpt-parser

Parser for .dpt files (dump parse tree) as generated by gfortran with the -fdump-parse-tree option

dummy_plug

Dummy Plug is a simple bus functional model library written by VHDL only.

edcl_server

Demonstration of UML and Nexys4-ddr board. Work in progress.

efuns

efuns is a re-write of emacs in ocaml written by Fabrice Le Fessant

ethernet_mac

Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL