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riscv-poky

Port of the Yocto Project to the RISC-V ISA

riscv_isa_formal_spec_in_bsv

A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)

riscv_jtag_server

rocket-chip

Rocket Chip Generator

siril

skychart

SkyChart / Cartes du Ciel Free software to draw sky charts

stellarium

Stellarium is a free GPL software which renders realistic skies in real time with OpenGL. It is available for Linux/Unix, Windows and macOS. With Stellarium, you really see what you can see with your eyes, binoculars or a small telescope.

symbiflow-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

sysver2ver

Converting System Verilog to plain Verilog using .xml dump from Verilator

tftpserver

A simple tftp server, in C

u-boot

"Das U-Boot" Source Tree

u-boot-riscv

Port of u-boot to RISCV based ariane core

ucsd-psystem-vm

Actively maintained fork of Peter Miller's UCSD P-System tools - Virtual machine

uhdm

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

usbhwthinclient4vm

Attempt to attach display/mouse/keyboard to VMWAVE virtual machine. HW device for this: Altera MAX10 FPGA dev kit "marsohod3"

vcdparser

vcd parser written in OCaml, adapted from the Python version by Eric Anderson

ver_front

Toy Verilog pre-processor in OCaml

verible

Verible provides a SystemVerilog parser, style-linter, and formatter.

vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

xc7k325t-blinky-nextpnr

xmas-labels

Brain-dead hack to address the Christmas Card labels problem

xml-light-windows

fork of Xml-light

xv6-riscv

Xv6 for RISC-V

yosys

Yosys Open SYnthesis Suite