Comments (1)
Simplify cache modules
However, Icache takes one clock on cache hit, need instruction prefetch to improve performance.
To infer block RAM, register output of ram is required.
On some context?, it may infer RAM by registering read address, however it is not recommended, so need at least one clock for registering output of cache ram to infer block ram. (still, need investigation.)
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Related Issues (20)
- Privilege mode transition in memory stage on trap handling HOT 1
- imprecise implementation of fence instruction. HOT 1
- Imprecise instret register
- Inference of memory block in BTB
- Delegation of exceptions to supervisor mode from machine mode.
- Supporting of N extensions
- Occurrence of interrupts and exceptions during bus accesses. HOT 2
- Arbitrate memory access from Instruction Bus and Data Bus
- Replace simple protocol for system bus with AHB-Lite.
- Extend physical address space to 34 bits
- Rename dcache_unit to load_store_unit.
- Unnecessary condition check on load hazard
- Correct spelling mistakes in projects
- Check alignment of operand address in AMO operations.
- Change interface of UART(uart_sender, uart_receiver) to UART 16550 compliant.
- Supervisor mode interrupt takes over machine mode interrupt
- Some byte in D$ entry are incorrect in some condition where SV32 enabled.
- Add context 1 to plic to support supervisor external interrupts in core0.
- Inference of memory block in cache module
- PLIC does not accept interrupts under certain circumstances
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