ktz-goel Goto Github PK

ahir

Algorithm to hardware compilation tools (e.g. C to VHDL).

avr-atmega16

Kshitiz Goel AGV ATmega codes

coetool

coetool is a cli or gui program to convert from .coe files (memory map for a ROM in an FPGA) to image files and the other way around, load an image and generate .coe file.

dynamicprefetch

A modification of the gem5 simulator for dynamic prefetching of data.

edgecloudsim

EdgeCloudSim: An Environment for Performance Evaluation of Edge Computing Systems

eseur-code-data

Code and data used to create the examples in "Evidence-based Software Engineering based on the publicly available data"

ethernet-interfacing-with-spartan-6

Using 100 BaseT expansion module from Numato. On Xilinx ISE Design Suite on verilog.

ethernet_fpga

fpga

starting FPGA on spartan 6 board

gpgpu-sim_distribution

GPGPU-Sim provides a detailed simulation model of a contemporary GPU running CUDA and/or OpenCL workloads and now includes an integrated (and validated) energy model, GPUWattch.

kshitiz_goel

Just another minimalist Jekyll theme which designed for technical writing blog.

ml605

packetsniffer

A simple packet sniffer written in Summer 2015 using Qt for the gui and Pcap to sniff ethernet packets. Written to learn a little about the networking stack and various protocols.

quic-bbr-ns-3

Integration of the BBR congestion control mechanism in the ns-3 QUIC module

udp_ip_stack

This repository contains a copy of the "1G eth UDP / IP Stack" opencores.org project(http://opencores.org/project,udp_ip_stack) and add a fully working mac layer for the Virtex 6 ML605 board. Moreover it provides a Qt benchmark software.

verilog-ethernet

Verilog Ethernet components