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arbiter

Round-robin arbiter verification in SystemVerilog

design-and-asic-implementation-of-32-point-fft-processor

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be bui

i2s

i2s core, with support for both transmit and receive

openofdm

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

systemverilog

System Verilog Presentation / example code I wrote to use as a template for future test benches

tensor2tensor-transformer-

Library of deep learning models and datasets designed to make deep learning more accessible and accelerate ML research.

verilog-i2s-transciever

I2S transciever implemented in Verilog HDL

vimos