laotou-v Goto Github PK

aes-processor

AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emulation Competition 2016.

chipwhisperer

ChipWhisperer - the complete open-source toolchain for side-channel power analysis and glitching attacks

cryptography

密码编码学算法学习

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

e203_hbirdv2

The Ultra-Low Power RISC-V Core

fpga-application-development-and-simulation

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

fpga-rocket-chip

Wrapper for Rocket-Chip on FPGAs

k-cipher

letsgo_1

Config files for my GitHub profile.

openc910

OpenXuantie - OpenC910 Core

opentitan

OpenTitan: Open source silicon root of trust

openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

platformio-core

PlatformIO is a professional collaborative platform for embedded development :alien: A place where Developers and Teams have true Freedom! No more vendor lock-in!

riscv-crypto

RISC-V cryptography extensions standardisation work.

sm2_core

opensource crypto IP core

sm3-verilog

sm3_core

sm4-sbox

Verilog Implementation of SM4 s-box

sm4-verilog

swerv_eh1

A directory of Western Digital’s RISC-V SweRV Cores

wujian100_open

IC design and development should be faster，simpler and more reliable

xiangshan

Open-source high-performance RISC-V processor