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Luis Ardila's Projects

dcc icon dcc

Digital signal processing using VHDL, Terasic's DE2i-150 FPGA Development Kit (CPU-FPGA PCIe link) and DCC AD/DA

dcc_adaptable icon dcc_adaptable

Digital signal processing using VHDL and Verilog, Filter coefficients are reloadable during run time via PCIe link. Terasic's DE2i-150 FPGA Development Kit (CPU-FPGA PCIe link) and DCC AD/DA

dcc_v_33 icon dcc_v_33

Adaptive LMS filter on DE2i-150 Development Board + DCC(AD/DA Data Conversion Card) Verilog

de2i_150_dcc icon de2i_150_dcc

Digital signal processing using VHDL and Terasic's DE2i-150 FPGA Development Kit and DCC AD/DA

fpga_conf icon fpga_conf

General script to configure FPGAs using the batch mode from Impact

hv_isegshq icon hv_isegshq

PyQt GUI to control and visualize the parameters on the HV power Supply Iseg SHQ 224M using Tango server

kicad-hdl icon kicad-hdl

Tools to convert Kicad intermediate netlist to HDL block diagram netlist

kipart icon kipart

Python package for generating multi-unit schematic symbols for KiCad from a CSV file.

mipi_csi_receiver_fpga icon mipi_csi_receiver_fpga

MIPI CSI-2 Camera Sensor Receiver verilog HDL implementation For any generic FPGA. Tested with IMX219 on Lattice MachXO3LF. 2Gbps UVC Video Stream Over USB 3.0 with Cypress FX3

netlistgen icon netlistgen

Sample project to generate netlist for ip cores and hdl sources

rolandmodeladriller icon rolandmodeladriller

Using the Roland Modela CNC MDX-20/15 for drilling glass substrates with Matlab GUI, provides aligning features with translation, rotational and scaling matrix

samplecode icon samplecode

This repository contains sample code for different Numato Lab products

sas_parsing icon sas_parsing

This is an easy Desktop application to parse the output of the statistics software SAS and produce tables with the desired info in .csv for visualization using a simple excel spreadsheet

star-ssd-rdo icon star-ssd-rdo

Firmware (VHDL) and Software for the readout electronics of the Silicon Strip Detector (SSD) at STAR - RHIC

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